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- W2736756578 abstract "Delta-sigma modulators (DSM) in conventional Fractional-N PLLs produce quantization noise and can't remove fractional spurs around the main frequency well. In order to reduce the spurs in Fractional-N synthesizers, a new Nested-PLL has been presented in this work. The proposed Fractional-N PLL consists of a conventional PLL as a frequency multiplier (*M) in feedback path that make fraction M/N along divider (N). In the other words the fraction M/N is achieved by a Nested-PLL instead of delta-sigma modulator. Therefore, spurs caused by delta-sigma modulator or pulse swallower is removed. The proposed Nested-PLL and its stability issues are addressed in this paper. Also to verify the proposed structure a prototype of the synthesizer with F ref =100MHz and F out =1GHz–1.3GHz designed and simulated systematically, and no fractional spurs are observed." @default.
- W2736756578 created "2017-07-31" @default.
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- W2736756578 date "2017-05-01" @default.
- W2736756578 modified "2023-09-28" @default.
- W2736756578 title "A new Fractional-N frequency synthesizer using Nested-PLL architecture" @default.
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- W2736756578 doi "https://doi.org/10.1109/iraniancee.2017.7985408" @default.
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