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- W2737390997 abstract "The design of systolic arrays has for the most part been an ad hoc or heuristic process. Dependence graph mapping methodologies provide a systematic approach for systolic array design. These techniques have previously been demonstrated primarily on simple examples such as matrix multiplication or discrete convolution. Their utility for more sophisticated problems is examined in this dissertation.The dependence graph mapping methods due to S. Rao were applied to the signal processing applications of Kalman filtering and prediction algorithms, discrete Fourier transform (DFT) algorithms, and fast Fourier transform (FFT) algorithms. The QR triangularization formulation for Kalman estimation proposed by M. Chen and K. Yao was used in the Kalman processor array research. Dependence graph mapping methodologies transform one single assignment algorithm to a processor array for that algorithm. The more complex algorithms examined were frequently better described as a sequence of stages with a single assignment algorithm for each stage. The techniques of dependence graph mapping can then be applied to each stage separately. The dependence graph mapping parameters for these mappings must be selected so that when the mappings for the various stages are combined into the complete array, the design objectives are satisfied.The use of dependence graph mapping for the derivation of existing Kalman estimation, DFT, and FFT systolic arrays was demonstrated. In addition, two new Kalman estimation arrays were developed. The first results in a slightly greater processor utilization then previously proposed arrays. Prior Kalman estimation arrays all share the characteristic of requiring long communication links for data feedback. The design criterion of eliminating all such links served as the basis for the choice of the dependence graph mapping parameters in the design of the second new Kalman estimation array. A new systolic array is also developed for the DFT which has improved throughput over existing arrays. The array requires N processors and a total of 4$sqrt{rm N}$ time slots from the first data input to the output of the last DFT output. Successive DFTs can be started every 2$sqrt{rm N}$ time slots." @default.
- W2737390997 created "2017-07-31" @default.
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- W2737390997 date "1990-01-03" @default.
- W2737390997 modified "2023-09-23" @default.
- W2737390997 title "Dependence graph mapping systolic array design for signal processing applications" @default.
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