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• W2738463133 abstract "In this brief, a hybrid-grained reconfigurable architecture (HReA) is introduced to process 13-Dwarfs. The proposed dynamically reconfigurable fabric consists of four 4 × 4 multi-functional processing elements array, where a hybrid-grained structure is proposed to combine a 32-bit data path with a 1-bit data path to accommodate multiple computing granularities in 13-Dwarfs. Aiming at the flexibility of the 13-Dwarfs calculation, a directional broadcasting scheme for multi-bank memory, a cache partitioning mechanism, and cache prefetching methods are proposed to further improve HReA performance via alleviating data and configuration bandwidth bottlenecks. The HReA is implemented on a 4.83 × 4.93 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> silicon with TSMC 65-nm LP1P8M CMOS technology and can efficiently perform 27 representative kernels from the 13-Dwarfs with 297 mW under 280-MHz working frequency." @default.
• W2738463133 created "2017-07-31" @default.
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• W2738463133 date "2018-03-01" @default.
• W2738463133 modified "2023-10-01" @default.
• W2738463133 title "HReA: An Energy-Efficient Embedded Dynamically Reconfigurable Fabric for 13-Dwarfs Processing" @default.
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• W2738463133 doi "https://doi.org/10.1109/tcsii.2017.2728814" @default.
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