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- W2741497249 abstract "This paper analyzes and designs a second order digital phase-locked loop (DPLL), and presents low power architecture for DPLL. The proposed architecture reduces the high power consumption of conventional DPLL, which results from using a read only memory (ROM) in implementation of the numerically controlled oscillator (NCO). The proposed DPLL utilizes a new design for NCO, in which no ROM is used. DPLL is designed and implemented using FPGA, consumes 237 mw, which means more than 25% saving in power consumption, and works at faster clock frequency compared to traditional architecture." @default.
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- W2741497249 date "2011-01-01" @default.
- W2741497249 modified "2023-09-27" @default.
- W2741497249 title "A Low Power Digital Phase Locked Loop With ROM-Free Numerically Controlled Oscillator" @default.
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