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- W2755662227 abstract "Electrostatic-discharge (ESD) immunity measurements of different layout manners in the drain-side of HV pLDMOS devices are investigated in this paper. Here, eleven kinds of drain-side npnpn arranged-types of pLDMOS-SCR parasitic structure are used to evaluate the layout impacts on ESD robustness. In this study, at first the layout type of N + region is continuous extended into the drain-side P + cathode. Secondly, the layout type of N + region is modulated by some discrete-distributed areas in the drain-side. From the experimental results, we can find that the ESD capability of the continuous extended and discrete distributed in the drain-side can be promoted, where all of the secondary breakdown current (I t2 ) values can be achieved 7 A. However, the discrete-distributed layout type has higher breakdown voltage (V BK ) than that of the reference group (the pure none modulated pLDMOS-SCR npnpn-type structure). Therefore, the discrete-distributed layout types show good electrical properties and reliability immunities." @default.
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- W2755662227 date "2017-09-01" @default.
- W2755662227 modified "2023-09-28" @default.
- W2755662227 title "Drain Side N<sup>+</sup> Layout Manners (npnpn Arranged-Type) on ESD Robustness in the 60-V pLDMOS-SCR" @default.
- W2755662227 cites W2058063843 @default.
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- W2755662227 doi "https://doi.org/10.4028/www.scientific.net/amm.870.401" @default.
- W2755662227 hasPublicationYear "2017" @default.
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