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• W2760677310 abstract "The rms timing jitter of a phase-locked loop (PLL) is calculated and minimized analytically from the VCO phase noise and the in-band phase noise plateau with and without digital baseband correction in an OFDM system. Subsequently, we present an integrated wideband frequency synthesizer in a 130 nm SiGe BiCMOS technology. An 8.7GHz-11.8GHz PLL using only one VCO is followed by a frequency sixtupler composed of a tripler and a doubler. The measured phase noise at 1 MHz offset from the 10 GHz PLL output frequency is below −108 dBc/Hz. For a 60 GHz OFDM system, this corresponds to an rms phase error of 1.5° and a PLL rms jitter of 70 fs after common phase error correction. The synthesizer chip occupies a chip area of 3.6 mm2 and draws 144 mA from a 3.3 V supply." @default.
• W2760677310 created "2017-10-06" @default.
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• W2760677310 date "2017-05-01" @default.
• W2760677310 modified "2023-09-26" @default.
• W2760677310 title "Design of a low-jitter wideband frequency synthesizer for 802.11ad wireless OFDM systems using a frequency sixtupler" @default.
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• W2760677310 doi "https://doi.org/10.1109/iscas.2017.8051000" @default.
• W2760677310 hasPublicationYear "2017" @default.
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