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- W2760841755 abstract "As transistor scaling is slowing down [1], other opportunities for ensuring continuous performance increase have to be explored. Field programmable gate arrays (FPGAs) are in the spotlight these days: not only due to their malleability and energy efficiency, but also because FPGAs have recently been integrated into the cloud [2]. The latter makes them available to everyone in need of the immense computing power and data throughput they can offer. However, one important issue needs to be resolved first - the time to compile an industrial-scale design for an FPGA must be drastically reduced. Researchers have been looking for ways to accelerate FPGA routing through parallelism, since routing is one of the most time-consuming compilation steps. However, the ideal solution has not been found yet. This paper provides a survey of parallel FPGA routers, with the aim to identify their strengths and weaknesses, thus suggesting directions to take in further efforts for acceleration." @default.
- W2760841755 created "2017-10-20" @default.
- W2760841755 creator A5045601003 @default.
- W2760841755 date "2017-09-01" @default.
- W2760841755 modified "2023-10-16" @default.
- W2760841755 title "Parallel FPGA routing: Survey and challenges" @default.
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- W2760841755 doi "https://doi.org/10.23919/fpl.2017.8056782" @default.
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