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- W2760992912 abstract "Objectives: The main aim of this paper is to implement 32Bit MIPS (Microprocessor Interlocked Pipeline Stages) RISC (Reduced Instruction Set Computer) Processor using Verilog HDL (hardware description language). Methods/Statistical analysis: The proposed algorithm analyzes the different stages of instruction decoding such as Instruction fetch module, Decoder module, Execution module and design theory based on 32Bit MIPS RISC Processor. In addition to that the algorithm uses pipelining concept which involves Instruction Fetch, Instruction Decode, Execution, Memory and Write Back modules of MIPS RISC processor based on 32Bit MIPS Instruction set in a single clock cycle. Findings: RISC is a processor which is intended to perform a tiny set of operations, to expand the rate (speed) of the processor. In general, the processor works with a huge number of instructions every second by bringing the information from the memory. In the event that the processor speed does not coordinate with memory access speed then hardware interlocks happen. In concurring with this there is one more issue called stalls because of instruction pipelining in the CPU design. The primary desire of this paper is to design and synthesize the MIPS processor by making utilization of register files and to insert the ALU forwarding unit in order to avoid the stalls and hardware interlocks. Application/Improvements: Based on the literature survey, the proposed method brings significant power efficiency improvements with enhanced performance and reduced power dissipation due to not only technology scaling but also a great deal of design efforts." @default.
- W2760992912 created "2017-10-20" @default.
- W2760992912 creator A5020788989 @default.
- W2760992912 creator A5071011712 @default.
- W2760992912 date "2017-03-01" @default.
- W2760992912 modified "2023-09-25" @default.
- W2760992912 title "ASIC design of MIPS based RISC processor for high performance" @default.
- W2760992912 cites W2021680312 @default.
- W2760992912 cites W2073198152 @default.
- W2760992912 doi "https://doi.org/10.1109/icnets2.2017.8067945" @default.
- W2760992912 hasPublicationYear "2017" @default.
- W2760992912 type Work @default.
- W2760992912 sameAs 2760992912 @default.
- W2760992912 citedByCount "5" @default.
- W2760992912 countsByYear W27609929122020 @default.
- W2760992912 countsByYear W27609929122021 @default.
- W2760992912 countsByYear W27609929122023 @default.
- W2760992912 crossrefType "proceedings-article" @default.
- W2760992912 hasAuthorship W2760992912A5020788989 @default.
- W2760992912 hasAuthorship W2760992912A5071011712 @default.
- W2760992912 hasConcept C111919701 @default.
- W2760992912 hasConcept C117280010 @default.
- W2760992912 hasConcept C126298526 @default.
- W2760992912 hasConcept C149635348 @default.
- W2760992912 hasConcept C156972235 @default.
- W2760992912 hasConcept C170595534 @default.
- W2760992912 hasConcept C173608175 @default.
- W2760992912 hasConcept C1793878 @default.
- W2760992912 hasConcept C201736964 @default.
- W2760992912 hasConcept C202491316 @default.
- W2760992912 hasConcept C2780728072 @default.
- W2760992912 hasConcept C41008148 @default.
- W2760992912 hasConcept C43521106 @default.
- W2760992912 hasConcept C49154492 @default.
- W2760992912 hasConcept C526435321 @default.
- W2760992912 hasConcept C77390884 @default.
- W2760992912 hasConcept C9390403 @default.
- W2760992912 hasConceptScore W2760992912C111919701 @default.
- W2760992912 hasConceptScore W2760992912C117280010 @default.
- W2760992912 hasConceptScore W2760992912C126298526 @default.
- W2760992912 hasConceptScore W2760992912C149635348 @default.
- W2760992912 hasConceptScore W2760992912C156972235 @default.
- W2760992912 hasConceptScore W2760992912C170595534 @default.
- W2760992912 hasConceptScore W2760992912C173608175 @default.
- W2760992912 hasConceptScore W2760992912C1793878 @default.
- W2760992912 hasConceptScore W2760992912C201736964 @default.
- W2760992912 hasConceptScore W2760992912C202491316 @default.
- W2760992912 hasConceptScore W2760992912C2780728072 @default.
- W2760992912 hasConceptScore W2760992912C41008148 @default.
- W2760992912 hasConceptScore W2760992912C43521106 @default.
- W2760992912 hasConceptScore W2760992912C49154492 @default.
- W2760992912 hasConceptScore W2760992912C526435321 @default.
- W2760992912 hasConceptScore W2760992912C77390884 @default.
- W2760992912 hasConceptScore W2760992912C9390403 @default.
- W2760992912 hasLocation W27609929121 @default.
- W2760992912 hasOpenAccess W2760992912 @default.
- W2760992912 hasPrimaryLocation W27609929121 @default.
- W2760992912 hasRelatedWork W1680705574 @default.
- W2760992912 hasRelatedWork W182515070 @default.
- W2760992912 hasRelatedWork W1971263764 @default.
- W2760992912 hasRelatedWork W2104456922 @default.
- W2760992912 hasRelatedWork W2148099609 @default.
- W2760992912 hasRelatedWork W2164026451 @default.
- W2760992912 hasRelatedWork W2760992912 @default.
- W2760992912 hasRelatedWork W2806352516 @default.
- W2760992912 hasRelatedWork W4310584696 @default.
- W2760992912 hasRelatedWork W4367172762 @default.
- W2760992912 isParatext "false" @default.
- W2760992912 isRetracted "false" @default.
- W2760992912 magId "2760992912" @default.
- W2760992912 workType "article" @default.