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- W2763484263 abstract "This paper reports a picosecond pulse receiver based on a three-stage divide-by-8 injection-locked frequency divider. The receiver operates for pulses with center frequency of 77 GHz and locks its output to the 9.6-GHz repetition rate with an effective locking range of 142 MHz. This receiver, which consumes 42 mW dc power, is used to demonstrate wireless clock synchronization with a 0.29ps RMS timing jitter and indicates an estimated sensitivity of −65.5 dBm in detecting picosecond pulses." @default.
- W2763484263 created "2017-10-20" @default.
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- W2763484263 date "2017-06-01" @default.
- W2763484263 modified "2023-09-26" @default.
- W2763484263 title "A fully integrated injection-locked picosecond pulse receiver for 0.29pS<inf>rms</inf>-jitter wireless clock synchronization in 65nm CMOS" @default.
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- W2763484263 doi "https://doi.org/10.1109/mwsym.2017.8058821" @default.
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