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- W2765228766 abstract "This chapter describes designing a three-phase clock and examines the use of combinational logic and extracting the Boolean equations. The chapter also describes optimizing the Boolean equations. The optimized equations can be quickly determined using Karnaugh Map techniques. Penultimate implementation of the combinational logic only requires four 2-input AND gates and three 2-input OR gates. Ultimate implementation of the combinational logic requires seven 2-input NAND gates. The chapter presents a figure for the implementation of Johnson counter or a ring counter, which at its most rudimentary level simply involves daisy-chaining D-type flip-flops together as a shift register, and feeding back the inverted output from the last “flop” to drive the input to the register chain. Johnson counter provides the outputs that are required to generate phase clocks, and these outputs follow a gray code sequence. It means that only one register—and therefore one output—changes state for each clock cycle so the outputs are “glitch-free” that can be quite useful in certain circumstances.." @default.
- W2765228766 created "2017-11-10" @default.
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- W2765228766 date "1998-01-01" @default.
- W2765228766 modified "2023-09-23" @default.
- W2765228766 title "Designing a Three-Phase Clock" @default.
- W2765228766 doi "https://doi.org/10.1016/b978-075069089-8/50020-7" @default.
- W2765228766 hasPublicationYear "1998" @default.
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