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- W2765718135 abstract "This paper presents a high drivability of full adder with less area and power consumption. This GDI based full adder is implemented by using both gate diffusion input (GDI) technique and pass transistor logic that leads to be a reduced area and power. To reducing the static power, ultralow power diode (ULPD) is used. The leakage current of this diode lies within the range of pA. The comparison has been done between existing systems like CMOS, CPL and hybrid full adders with proposed full adder. All full adders are designed with gpdk 0.18 um in Cadence Virtuoso schematic, and simulations are done in a Spectre Simulator." @default.
- W2765718135 created "2017-11-10" @default.
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- W2765718135 date "2017-07-01" @default.
- W2765718135 modified "2023-09-27" @default.
- W2765718135 title "Design of area and power efficient full adder in 180nm" @default.
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- W2765718135 doi "https://doi.org/10.1109/netact.2017.8076791" @default.
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