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- W2765722198 abstract "The Mayan binary multiplier is an architecture to simplify and optimize the multiplication implemented in FPGAs. This architecture is based on the Maya multiplication method or Tzeltal. The architecture takes advantage of the parallelism of FPGAs grouping multipliers for generating the partial products. The multiplication is accelerated by decreasing the number of sums to be performed. This new approach provides properties that improve arithmetic calculations." @default.
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- W2765722198 date "2016-09-01" @default.
- W2765722198 modified "2023-09-23" @default.
- W2765722198 title "Architecture design to optimize multipliers in FPGAs based on Maya multiplying method" @default.
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- W2765722198 doi "https://doi.org/10.1109/conescapan.2016.8075212" @default.
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