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- W2766041087 abstract "Next generation high speed network/communication packages require much larger die sizes and increased ball counts (>3000) to meet high speed, high input/output (I/O) functionality and improved reliability performance. Demand for such high speed large flip chip packages create an opportunity for highly integrated multi-chip modules (MCM’s) and 2.5D/3D silicon (Si) interposer packages which are gradually emerging to meet these requirements. Achieving both increased margins in the power delivery network and increased functionality in next generation high speed network/communication applications requires extremely efficient, low loss package designs with body sizes 50×50mm or larger. One of the biggest challenges for such large die, large body packages is how effectively the assembly risk can be mitigated while fulfilling long term package reliability and functionality. The work presented in this paper describes key factors for mitigating several assembly related issues in the industry, including package warpage/co planarity, and the identification of the optimum processes and materials for successfully manufacturing large body flip chip packages with high assembly yields. As the body sizes and die sizes increase, the chip-to-package interaction failure risk increases significantly due to a larger distance to neutral point (DNP). Typical assembly risks are extreme low-k (ELK) delamination (white bumps) during the chip joining process, bump tearing or cracking, underfill delamination, and warpage issues. A comprehensive experiment was carried out to achieve the objective of the work. A test vehicle was developed using a 21×22mm2, flip chip copper (Cu) column bumped die placed onto a 50×50mm body size, using a multi-layer substrate with full array BGA footprint and ample passive components in the package. Processes were developed to optimize assembly yield and package reliability, including an extensive board level reliability test. Assembly materials were selected to achieve excellent assembly yield, high thermo-mechanical reliability, and increased package functionality." @default.
- W2766041087 created "2017-11-10" @default.
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- W2766041087 date "2017-08-29" @default.
- W2766041087 modified "2023-09-27" @default.
- W2766041087 title "Large Flip Chip Assembly Challenges and Risk Mitigation Process" @default.
- W2766041087 cites W2082637007 @default.
- W2766041087 doi "https://doi.org/10.1115/ipack2017-74026" @default.
- W2766041087 hasPublicationYear "2017" @default.
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