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- W2772234110 abstract "This paper presents a Soft-Edge Error-Detecting Flip-Flop (SEED FF), which can be used in Ultra-Low-Voltage (ULV) digital circuits to address timing variation problems with a lower timing error correction rate. The master latch's clock edge of a timing error detecting flip-flop is delayed so that it has not only the timing error detection capability but also a narrow transparency window. HSPICE simulations show that the performance of S386 of ISCAS'89 using SEED FF is improved by 31.36% at 0.35 V compared with the traditional error detecting flip-flops." @default.
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- W2772234110 date "2017-10-01" @default.
- W2772234110 modified "2023-09-26" @default.
- W2772234110 title "Soft-Edge error-detecting flip-flop for lowering error-correction-rate under ultra-low voltage" @default.
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- W2772234110 doi "https://doi.org/10.1109/edssc.2017.8126424" @default.
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