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- W2775245113 abstract "The wire-length of vertically stacked ICs plays a vital role. The wire-length is minimized by using differential evolutionary algorithms withIBM Benchmark inputs. Moreover this wire length is minimized with the respect to the length of the Through Silicon via (TSVs). As a result, the wire-length has been minimized using this algorithm with various parameters. Experimental result shows that the total wirelength can be reduced." @default.
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- W2775245113 date "2017-04-01" @default.
- W2775245113 modified "2023-09-29" @default.
- W2775245113 title "Minimizationof wirelength in 3d IC routing by using differential evolution algorithm" @default.
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- W2775245113 doi "https://doi.org/10.1109/iceice.2017.8191950" @default.
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