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- W2775409815 abstract "This work presents an in-depth analysis of double gate TFET architecture with pocket region i.e. p-n-i-n TFET considering the gate misalignment effects. The variations in device electrostatic characteristics due to such process induced effects have been analyzed through analytical model. The impact of gate misalignment can be seen at drain/channel junction in terms of underlap region created near it. The drain current model is developed for variation in gate and drain bias in all operational regimes i.e. accumulation, depletion and inversion and has been validated through ATLAS Device Simulator." @default.
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- W2775409815 date "2017-08-01" @default.
- W2775409815 modified "2023-09-26" @default.
- W2775409815 title "Modeling the impact of gate misalignment in tunnel field effect transistors" @default.
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- W2775409815 doi "https://doi.org/10.1109/icmdcs.2017.8211537" @default.
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