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- W2778926082 abstract "Failures may often occur in the packaged power terminals (PPTs) of the heater modules during harsh wafer baking process. The dominant failure factor is a high temperature. Hence, the performances of the PPTs should be explored under multiphysics environment to develop robust heater modules. In this study, FEA electrical-thermal-structural models of the PPTs are developed and experimentally validated. Various parametric influences on the thermal and structural performance of PPTs are investigated employing FEA electrical-thermal-structural models. The study has shown that the substrate thickness was a dominant parameter affecting the PPT performance." @default.
- W2778926082 created "2018-01-05" @default.
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- W2778926082 date "2017-09-01" @default.
- W2778926082 modified "2023-09-26" @default.
- W2778926082 title "Electrical-thermal-structural performance of packaged power terminals for wafer baking" @default.
- W2778926082 cites W2081281036 @default.
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- W2778926082 doi "https://doi.org/10.1109/therminic.2017.8233835" @default.
- W2778926082 hasPublicationYear "2017" @default.
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