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- W2779370380 abstract "A cominon voltage controlled oscillator (VCO) architecture used in the phase locked loop (PLL) is the ring oscillator because it has wider tuning range and consume less area on chip. Due to technology scaling trend and communication system evolution,the demand of low power consumption is become one of the major criteria in integrated circuit (IC) design engineer perspective. Forward bode bias (FBB) used indigital and low-power analog integrated circuits to adjust the threshold voltage of complementary metal-oxide-semiconductor (CMOS) transistors. Thus, a forward bodybiased approach is proposed to be implemented in designing the ring oscillator due to it capability to reduce threshold voltage of the transistor and leads to a low powerconsumption circuit. This project presents a low power ring oscillator designed for wireless application at 3 GHz. A 5-stage single-ended ring oscillator is designed usingforward body bias technique in a standard 0.13 μm CMOS technology. The simulation is perfoi:med using ELDO Spice simulator from Mentor Graphics. With supply voltage of 0.8 V, the power dissipation is 167.03 μWand the phase noise is -72.88 dBc/Hz at 1 MHz. The proposed ring oscillator with new delay cell layout occupied 22.4 x 25.6 pm2" @default.
- W2779370380 created "2018-01-05" @default.
- W2779370380 creator A5014004954 @default.
- W2779370380 date "2017-01-01" @default.
- W2779370380 modified "2023-09-24" @default.
- W2779370380 title "Design Of Ring Oscillator Using Forward Body BIAS (FBB) Technique" @default.
- W2779370380 hasPublicationYear "2017" @default.
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