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- W2780029225 abstract "We propose a column-based split cell-VSS (CS-CVSS) data-aware write-assisted (DAW A) 9T ultra-low voltage SRAM with enhanced read sensing margin in 28nm FDSOI technology. The proposed write-assist technique (CS-CVSS and DAWA) improve both half-select SNM and write margin. The proposed 3T low leakage read port enhances read sensing margin by minimizing bitline leakage through negative gate to source voltage. A 16kb 9T SRAM test chip demonstrates VDDMIN-Write improvement of 0.39 V and VDDMIN-Read of 0.25 V with 1.57 ps read access time. The energy of 6.72 pJ is achieved at 0.5 V." @default.
- W2780029225 created "2018-01-05" @default.
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- W2780029225 date "2017-11-01" @default.
- W2780029225 modified "2023-09-24" @default.
- W2780029225 title "A 16kb column-based split cell-VSS, data-aware write-assisted 9T ultra-low voltage SRAM with enhanced read sensing margin in 28nm FDSOI" @default.
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- W2780029225 doi "https://doi.org/10.1109/asscc.2017.8240242" @default.
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