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- W2780328059 abstract "In order to find a way to solve the contradiction among storage space, transmission capacity and the data volume in the embedded systems, a data compression scheme based on block matching with an identifier is presented by using the technology of digital integrated circuit. The scheme can achieve lossless real-time data compression and reduce the volume of the data. Through statistical analysis on the data source, the authors can obtain that such a scheme has many advantages in real-time performance, a complication of implement, efficiency and practicability. So the digital circuit is considered as a method which can present the encoding process. With the help of QUARTUS II, they combine Verilog and schematic to finish the design hierarchically and code the decompression program by using C language for comparison. The accuracy and efficiency of the circuit are verified with simulation and relevant experiments. The average compression rate is 52.3% with 12 MHz clock frequency and the compression speed on average is 352% faster than the one by using block-match software algorithm. The scheme would have good performance in many embedded systems." @default.
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- W2780328059 date "2018-01-18" @default.
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- W2780328059 title "Scheme for variable‐frequency digital circuit with data compression based on block‐match process" @default.
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- W2780328059 doi "https://doi.org/10.1049/iet-cds.2017.0468" @default.
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