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- W2782079150 abstract "In this paper an efficient fused three operand floating point add-subtract unit is designed using Binary Signed Digit (BSD) adder. BSD adder-subtractor improves overall speed of addition due to its carry limited operation. BSD adder delay reduces by 28% and 17% compared to carry save adder (CSA) and ripple carry adder (RCA) respectively. Three operand adder performs two additions in a single unit which reduces overall critical path compared to discrete and two term computation. It shows 25% reduction in delay and 14% reduction in area compared to three term computation using discrete unit. It will be an enhanced way-out for most of the algorithms with multiple additions." @default.
- W2782079150 created "2018-01-12" @default.
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- W2782079150 date "2017-11-01" @default.
- W2782079150 modified "2023-10-09" @default.
- W2782079150 title "Three operand fused floating point add-subtract unit using redundant adder" @default.
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- W2782079150 doi "https://doi.org/10.1109/tencon.2017.8228066" @default.
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