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- W2783174073 abstract "This paper presents a [Formula: see text]-enabled output-capacitor-free CMOS low-dropout (LDO) regulator with fast transient response for cost-effective system-on-chip (SoC) power management applications with elevated-[Formula: see text] supply. All the MOS transistors used in the proposed LDO regulator are low voltage (LV) MOSFETs, hence saving the high voltage devices fabrication cost required in a conventional design. Two LV power transistors are cascaded in the power train. A mid-rail regulator is used to generate [Formula: see text] voltage for the power transistors as well as the main error amplifier to guarantee safe operation. The mid-rail regulator employs stacking transistors to handle the high supply voltage. Moreover, Miller compensation with adaptive biasing is used to achieve good stability and fast transient response. A proof-of-concept design is fabricated in a standard 0.18-[Formula: see text]m CMOS process which achieves 3.3–3.6[Formula: see text]V nominal input, 3.1[Formula: see text]V nominal output and 100[Formula: see text]mA loading capability with all the transistors being 1.8[Formula: see text]V MOSFETs." @default.
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- W2783174073 date "2018-04-26" @default.
- W2783174073 modified "2023-10-13" @default.
- W2783174073 title "A 2 × VDD-Enabled Output-Capacitor-Free Low-Dropout Regulator with Fast Transient Response for Low-Cost System-on-Chip" @default.
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- W2783174073 doi "https://doi.org/10.1142/s0218126618501438" @default.
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