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- W2783223289 abstract "In this paper, we discuss a technique for selective GeO x -scavenging which creates a GeO x -free interfacial layer (IL) on Si 1−x Ge x substrates. This process reduces interface trap density (N it ) and increases high-field hole mobility in Si 1−x Ge x pFETs. In addition, we identify the existence of electronic defect levels close to the Si 1−x Ge x band edges associated with the Ge surface concentration at the Si 1−x Ge x /IL interface. These electronic defects act as carrier scattering centers severely degrading the channel mobility and modulate the device threshold voltage. By successfully eliminating the GeO x component in the IL and electronic defects states at the Si 1−x Ge x /IL interface, high channel carrier mobility over a wide range of inversion carrier density in compressively-strained Si 1−x Ge x channel pFETs is demonstrated." @default.
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- W2783223289 date "2017-10-01" @default.
- W2783223289 modified "2023-09-26" @default.
- W2783223289 title "Interface engineering of Si<inf>1−x</inf>Ge<inf>x</inf> gate stacks for high performance dual channel CMOS" @default.
- W2783223289 doi "https://doi.org/10.1109/asicon.2017.8252540" @default.
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