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- W2784538817 abstract "In this paper we present an efficient design for self-checking fast adders data paths. We investigate the implementation of concurrent error detection fast adders: carry look-ahead, Carry skip, Carry-select and Conditional-Sum adders. To achieve a low overhead, low power design, we use hybrid-CMOS logic style and combine Conventional CMOS and CMOS Pass transistor Logic (CPL). The proposed schemes are Totally Self-Checking (TSC). They are fully differential and checked by dual-rail and parity codes." @default.
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- W2784538817 date "2013-10-23" @default.
- W2784538817 modified "2023-09-26" @default.
- W2784538817 title "HYBRID-CMOS LOGIC STYLE DESIGN FOR FAST SELF-CHECKING ADDERS DATA PATHS" @default.
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- W2784538817 doi "https://doi.org/10.24297/ijct.v10i6.7025" @default.
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