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• W2785330810 abstract "This paper presents a time-to-digital converter (TDC) architecture with reduced hardware suitable for timing built-in self-test (BIST) / built-out self-test (BOST) implementation. In order to reduce the number of buffers and D Flip-Flops (DFFs) in a conventional Flash TDC or Vernier TDC, successive approximation is applied to construct a successive approximation register (SAR) TDC. Besides, Vernier TDC has been added as the sub-circuit to form a (two-step SAR) + (SAR-Vernier) TDC architecture. Its self-calibration method for the linearity improvement is shown. We also propose to use a trigger circuit (originally used in an equivalent-time sampling oscilloscope) in front of the SAR TDC which enables to measure the timing effectively when two timing inputs are single-shot as well as repetitive clocks." @default.
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• W2785330810 date "2017-11-01" @default.
• W2785330810 modified "2023-10-18" @default.
• W2785330810 title "SAR TDC Architecture with Self-Calibration Employing Trigger Circuit" @default.
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• W2785330810 doi "https://doi.org/10.1109/ats.2017.29" @default.
• W2785330810 hasPublicationYear "2017" @default.
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