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• W2788245290 abstract "As part of the Scottish Collaborative Initiative in Optoelectronic Sciences (SCIOS) we have been developing an optoelectronic parallel data sorter as a technology demonstrator [1]. This system is based on 32 x 32 arrays of smart pixels produced by flip-chip solder bump assembly of InGaAs/GaAs MQW modulator/detectors with Si CMOS electronics. These devices are linked by an optical system which implements a perfect shuffle interconnection. The functionality of each of the processing nodes is selected by a combination of global electronic control signals and local optical control information which is circulated along with the data. The system aims at a clock frequency of 100 MHz which would give a sorting capacity of up to 1024 16 bit words in less than 20 µs. This corresponds to an I/O data rate of 200 Gbit/s for each of the chips in the system. The programme also includes the construction of a smaller 16-channel test system based on 4 x 4 smart pixel arrays. This paper present progress on the construction and initial tests of both these demonstrators." @default.
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• W2788245290 date "1997-01-01" @default.
• W2788245290 modified "2023-09-27" @default.
• W2788245290 title "Development of an Optoelectronic Parallel Data Sorter based on CMOS/InGaAs Smart Pixel Arrays" @default.
• W2788245290 doi "https://doi.org/10.1364/oc.1997.otha.4" @default.
• W2788245290 hasPublicationYear "1997" @default.
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