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• W2788697299 abstract "A low-voltage (1.3V), 64 Mbit Ferroelectric Random Access Memory using a 1-transistor, 1-capacitor (1T1C) cell is demonstrated. This is the largest FRAM memory demonstrated to date. The memory is constructed using a state-of-the-art 130 nm transistor and a five-level Cu/FSG interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate oxide, low-voltage logic process. Address access time for the memory is less than 30 ns while consuming 0.57 mW/MHz at 1.37 V. An eFRAM density of 1.13 Mb/mm/sup 2/ is achieved with a cell size of 0.54 /spl mu/m/sup 2/ and capacitor size of 0.25 /spl mu/m/sup 2/." @default.
• W2788697299 created "2018-03-06" @default.
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• W2788697299 date "2004-03-02" @default.
• W2788697299 modified "2023-09-27" @default.
• W2788697299 title "A 64 Mbit embedded FeRAM utilizing a 130 nm, 5LM Cu/FSG logic process" @default.
• W2788697299 cites W2134983598 @default.
• W2788697299 doi "https://doi.org/10.1109/vlsic.2003.1221194" @default.
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