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- W2788753311 abstract "This paper proposes a new NAND flash memory and related novel circuit techniques that suppress the program disturb and realize a smaller cell size with minimum array noise. The memory cell realizes a LOCOS width reduction of 20%. This architecture is essential for a scaled STI cell because of the improved program disturb. The proposed column latch and Vcc-bitline shield sensing method enable excellent noise immunity and decrease the Vth distribution from 1.2 V to 0.6 V. They also improve device reliability." @default.
- W2788753311 created "2018-03-06" @default.
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- W2788753311 date "2002-11-27" @default.
- W2788753311 modified "2023-10-17" @default.
- W2788753311 title "A negative Vth cell architecture for highly scalable, excellently noise immune and highly reliable NAND flash memories" @default.
- W2788753311 cites W2114803257 @default.
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- W2788753311 doi "https://doi.org/10.1109/vlsic.1998.688097" @default.
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