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- W2790787187 abstract "Low Power technologies are increasingly important, driven by the mobile device, IoT market, and the energy-saving. FD-SOI technology becomes more popular after few products successfully introduced in this process. It shows more possible methods to reduce the chip power consumption. This paper presents physical design of a Low Power SoC chip. The FD-SOI benchmark experience and customized IP design experience help to reduce the implementation schedule. We have developed dedicated 28nm FD-SOI IPs: USB2.0, MIPI DPHY, Audio CODEC, and the Low-power Memory. The physical implementation of the chip has been completed within 2 months." @default.
- W2790787187 created "2018-03-29" @default.
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- W2790787187 date "2017-10-01" @default.
- W2790787187 modified "2023-09-25" @default.
- W2790787187 title "Physical implementation of low power SoC chip based on SEC 28nm FDS" @default.
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- W2790787187 doi "https://doi.org/10.1109/s3s.2017.8309210" @default.
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