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- W2791245897 abstract "This paper presents the VLSI architecture of a low-latency and high-throughput sorted-QR decomposition (SQRD) engine for multiple-input multiple-output (MIMO) communication systems. In order to achieve a high processing throughput, the proposed design is architected based on a novel pipelined Givens rotation (GR) structure comprising of multi-dimension COordinate rotation DIgital computer (CORDIC) (MD-CORDIC) processing elements (PEs). Moreover, this design delivers the vector norm and conducts the sorting operation as a by-product of the vectoring operation on the execution flow of the CORDIC process. Therefore, excessive overheads for norm-calculation and sorting are excluded, and thus the latency is greatly reduced and throughput is enhanced. In addition, the proposed SQRD engine is operating directly on the complex-valued channel matrix to avoid the matrix augmentation caused by the real-valued decomposition of the channel matrix. This design has been synthesized, placed and routed, and the post-layout estimation results have shown that the processing throughput of the proposed SQRD architecture achieves an approximately 2[Formula: see text] improvement compared to the prior arts." @default.
- W2791245897 created "2018-03-29" @default.
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- W2791245897 date "2018-08-23" @default.
- W2791245897 modified "2023-09-24" @default.
- W2791245897 title "Architectural Optimizations for a High-Throughput Sorted QR Decomposition Circuit in MIMO Communication Systems" @default.
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- W2791245897 doi "https://doi.org/10.1142/s0218126618502201" @default.
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