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• W2796008788 abstract "High-speed thermal imaging is necessary in many applications. However, the traditional column-wise readout implementations reduce the achievable frame rate. Also, analog integration for each individual pixel is not possible without sacrificing pixel area. In this brief, we present an implementation of a fast and low-power pixel-wise readout circuit scheme with a digital integration method using 65-nm standard CMOS technology. The power consumption of the readout circuit is up to $15~mu{text{W}}$ and the layout area is $100~{mu }text{m} {times } 100~{mu }text{m}$ . Furthermore, we analyze our design for non-idealities, such as noise and process mismatches using a circuit simulator." @default.
• W2796008788 created "2018-04-13" @default.
• W2796008788 creator A5017724340 @default.
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• W2796008788 date "2018-05-01" @default.
• W2796008788 modified "2023-09-24" @default.
• W2796008788 title "Implementation of a Fast and Low-Power Thermopile Readout Circuit Arrangement for Array Processors" @default.
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• W2796008788 doi "https://doi.org/10.1109/tcsii.2018.2821898" @default.
• W2796008788 hasPublicationYear "2018" @default.
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