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• W2799163379 abstract "Timing anomalies in a system on a chip are one of the most common causes of functional misbehaviors. They are usually hard to find and poses a potential quality risk to the design and implementation of the system. Such anomalies might appear when high-volume validation is performed in the design, which usually takes place at advanced stages of the validation process and close to the product release qualification. In this paper, we propose a methodology to uncover potential timing problems using synthetic test patterns at the beginning of the post-silicon validation process, thus accelerating the timing bugs finding and improving the quality of the samples to be delivered to the customers." @default.
• W2799163379 created "2018-05-07" @default.
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• W2799163379 date "2018-03-01" @default.
• W2799163379 modified "2023-09-27" @default.
• W2799163379 title "Post-silicon validation based on synthetic test patterns for early detection of timing anomalies" @default.
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• W2799163379 doi "https://doi.org/10.1109/latw.2018.8347237" @default.
• W2799163379 hasPublicationYear "2018" @default.
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