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- W2800560412 abstract "A simulation study using thin (∼10 nm) HfO 2 PGP FDSOI NCFET based gates is presented. The study has been performed on devices having 20 nm metal gate length with supply voltage varying from 0.5 V to 0.9 V. The circuits studied were 3-stage ring oscillator, NAND-2 and NOR-2 gates. The study showed significant enhancement in the performance in HfO 2 FDSOI NCFET based gates at reduced power consumption which is −66% when compared to that of FDSOI MOSFET based gates. The power-delay product of HfO 2 FDSOI NCFET based gates was found to be significantly lower (∼24%) in comparison to baseline FDSOI MOSFET based gates. The effect of increasing fan-in and fan-out on the performance of logic gates has also been discussed in the paper." @default.
- W2800560412 created "2018-05-17" @default.
- W2800560412 creator A5059935247 @default.
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- W2800560412 date "2018-03-01" @default.
- W2800560412 modified "2023-09-24" @default.
- W2800560412 title "Potential of thin (∼10 nm) HfO<inf>2</inf> ferroelectric FDSOI NCFET for performance enhancement in digital circuits at reduced power consumption" @default.
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- W2800560412 doi "https://doi.org/10.1109/ulis.2018.8354775" @default.
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