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• W2801370963 abstract "The economics of CMOS scaling remain lucrative with 7-nm mobile SoCs expected to be commercialized in 2018. Driven by careful design/technology co-optimization, modest reduction in fin, gate, and interconnect pitch as well as process inn-ovations continue to offer compelling node-to-node power, performance, area, and cost benefits to advance logic and SRAM to the next foundry node. However, analog/mixed-signal circuits do not fully realize these improvements. They become more cumbersome to design, having worse parasitic resistance and capacitance, stronger layout-dependent effects, and layout growth in some situations. Furthermore, early adopters of these cutting-edge finFET nodes must cope with the complications of design concurrent with technology development for shorter product time-to-market. We provide an overview of the key process technology elements enabling 7 nm and beyond to address analog/mixed-signal design challenges. From this insight, we offer layout guidelines aimed to reduce design vulnerability to technology and model immaturity." @default.
• W2801370963 created "2018-05-17" @default.
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• W2801370963 date "2019-04-01" @default.
• W2801370963 modified "2023-09-26" @default.
• W2801370963 title "Analog/Mixed-Signal Design Challenges in 7-nm CMOS and Beyond" @default.
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• W2801370963 doi "https://doi.org/10.1109/cicc.2019.8780346" @default.
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