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- W2801470577 abstract "A low-power 1GS/s hybrid analog-to-digital converter (ADC) for portable wireless applications is described. The first stage of the subranging architecture contains a 3-bit flash ADC with offset calibration. Its second stage employs a 5-bit 4-channel time-interleaved (TI) comparator-based asynchronous binary search (CABS) ADC. A merged sample-and-hold and capacitive digital-to-analog converter (SHDAC) samples the input, and generates the residue voltage for the subranging operation in each channel. The error on the residue voltage from the parasitic capacitances is cancelled through a linearity correction method. Design considerations of the amplifier in the unity-gain buffer and bandwidth mismatches between TI channels are studied and exemplified with simulation results. A prototype ADC chip was fabricated in 130nm CMOS technology for experimental verification of the concepts. Evaluations of operation with 6-bit resolution at 1GS/s demonstrate a measured ENOB above 5.26 up to the Nyquist frequency with a power consumption of 10.5mW from a 1.2V supply." @default.
- W2801470577 created "2018-05-17" @default.
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- W2801470577 date "2018-05-01" @default.
- W2801470577 modified "2023-09-24" @default.
- W2801470577 title "Design Considerations and Experimental Verification of a 10.5mW 1GS/s Hybrid ADC for Portable Wireless Devices" @default.
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- W2801470577 doi "https://doi.org/10.1109/iscas.2018.8351660" @default.
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