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- W2801766250 abstract "Demonstration Setup: We will bring Braindrop, a mixed-signal neuromorphic chip that is configured to perform arbitrary computations using the Neural Engineering Framework (NEF). Fabricated in a 28-nm FDSOI process, Braindrop has 4,096 silicon neurons whose design we optimized for nonlinear function approximation (Fig. 1). Our optimization procedure consists of a pre-fabrication phase and a run-time phase. In the pre-fabrication phase, transistors are sized to introduce an intermediate amount of heterogeneity into the neurons' tuning curves: Not so little that spiking-thresholds bunch up in the middle of the function's domain and not so much that spiking-thresholds mostly fall outside the function's domain. In the run-time phase, the outliers—neurons that never spike or always spike—are rescued by adjusting programmable bias currents appropriately. We explored various choices of the number of programmable bias-current levels and the amount of transistor-mismatch during the design phase to determine the combination that yielded the highest number of good neurons. To facilitate design-space exploration, we developed a SPICE-derived compact model of the dependence of tuning-curve heterogeneity on transistor-mismatch." @default.
- W2801766250 created "2018-05-17" @default.
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- W2801766250 date "2018-05-01" @default.
- W2801766250 modified "2023-09-25" @default.
- W2801766250 title "Live Demonstration: Optimizing an Analog Neuron Circuit Design for Nonlinear Function Approximation" @default.
- W2801766250 doi "https://doi.org/10.1109/iscas.2018.8351572" @default.
- W2801766250 hasPublicationYear "2018" @default.
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