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• W2802336186 abstract "Towards gate-all-around (GAA) FETs, we present the top-down realization of vertical Ge nanowires (NWs) with defect-free sidewall and perfect anisotropy. The NW patterns are transferred by a novel inductively coupled plasma reactive ion etching (ICP-RIE) technique. With optimized etching conditions, sub-60 nm diameter Ge nanowires are guaranteed while mitigating micro-trenching and under-cutting effects. To further shrink the NW diameter, digital etching is followed including multiple cycles of self-limited O2 plasma oxidation and diluted HF rinsing. O2 plasma is also utilized for surface passivation in Ge MOScaps to improve the high-k/Ge interface. These NWs form the base of vertical transistors which are simulated by TCAD tools here. The processing techniques proposed in this work provide a viable option for low power vertical Ge and GeSn NW transistors." @default.
• W2802336186 created "2018-05-17" @default.
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• W2802336186 date "2018-03-01" @default.
• W2802336186 modified "2023-09-26" @default.
• W2802336186 title "Realization of vertical Ge nanowires for gate-all-around transistors" @default.
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• W2802336186 doi "https://doi.org/10.1109/ulis.2018.8354771" @default.
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