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- W2802394310 abstract "This paper studies the process scalability of pulse-mode CMOS circuits for analog 2-D convolution in computer vision systems. A simple, scalable architecture for an integrate and fire neuron is presented for implementing weighted addition of pulse-frequency modulated (PFM) signals. Sources of error are discussed and modeled in a detailed behavioral simulation and compared with equivalent transistor-level simulations. Next, the design of a 180-nm PFM chip with programmable weights is presented, and full image convolutions are demonstrated with the analog hardware. Preliminary chip measurements for a 45-nm implementation are also included to demonstrate process scalability. Design considerations for porting this architecture to nanometer processes, including FinFET technologies, are then discussed. This paper concludes with a simulation study on scaling down to 10 nm using a predictive technology model." @default.
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- W2802394310 date "2018-09-01" @default.
- W2802394310 modified "2023-09-24" @default.
- W2802394310 title "Process Scalability of Pulse-Based Circuits for Analog Image Convolution" @default.
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- W2802394310 doi "https://doi.org/10.1109/tcsi.2018.2821691" @default.
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