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- W2805141557 abstract "Low power less area bypassing based multipliers proposed on the bases of modified XOR gate in low cost low power bypassing based multiplier. On the bases of different tested samples our proposed design has average 49.41% less area, 13.6% reduced power dissipation, 2.36% less delay and 20.89% less power delay product in comparison to different types of multiplier for 4×4 and 8×8 bit." @default.
- W2805141557 created "2018-06-13" @default.
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- W2805141557 date "2017-11-01" @default.
- W2805141557 modified "2023-09-25" @default.
- W2805141557 title "Low-power less-area bypassing-based multiplier design" @default.
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- W2805141557 doi "https://doi.org/10.1109/icici.2017.8365186" @default.
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