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- W2805969917 abstract "The excellent error correction performance of Low-Density Parity Check code has made it widely used in many modern communication systems, including space communication system. This paper describes a design and FPGA implementation of a quasi-cyclic LDPC decoder based on Min-Sum Algorithm. The partially parallel design solves the contradiction between the consumption of hardware resource and decoding efficiency. The decoder achieves up to a BER of 10−3 at 4 dB, and a throughput of 300 Mbps per iteration for a code length of 8176." @default.
- W2805969917 created "2018-06-13" @default.
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- W2805969917 date "2018-06-07" @default.
- W2805969917 modified "2023-09-27" @default.
- W2805969917 title "Design and FPGA Implementation of a Quasi-Cyclic LDPC Decoder" @default.
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- W2805969917 doi "https://doi.org/10.1007/978-981-10-6571-2_222" @default.
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