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- W2806544020 abstract "To close the ever widening verification gap, new powerful solutions are strictly required. One such promising approach aims in continuing verification tasks after production of a chip during its lifetime. This approach is called self-verification. However, for realizing self-verification tasks on-chip, verification packages have to be developed. In this paper, we propose verification package SAT-Lancer. SAT-Lancer is a compact Boolean Satisfiability (SAT) solver and has been implemented entirely on HW with the capability of solving any arbitrary SAT-instance. At the heart of SAT-Lancer is a scalable memory model, which can be adjusted to given memory constraints and allows to store the SAT-instance most effectively. In comparison to previous HW SAT-solvers, SAT-Lancer utilizes significant less area and can handle order of magnitude larger SAT-instances." @default.
- W2806544020 created "2018-06-13" @default.
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- W2806544020 date "2018-05-30" @default.
- W2806544020 modified "2023-09-23" @default.
- W2806544020 title "SAT-Lancer" @default.
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- W2806544020 doi "https://doi.org/10.1145/3194554.3194643" @default.
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