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• W2806806218 abstract "Fault tolerance is of great importance for big data systems. Although several software-based application-level techniques exist for fault security in big data systems, there is a potential research space at the hardware level. Big data needs to be processed inexpensively and efficiently, for which traditional hardware architectures are, although adequate, not optimum for this purpose. In this paper, we propose a hardware-level fault tolerance scheme for big data and cloud computing that can be used with the existing software-level fault tolerance for improving the overall performance of the systems. The proposed scheme uses the concurrent error detection (CED) method to detect hardware-level faults, with the help of Scalable Error Detecting Codes (SEDC) and its checker. SEDC is an all unidirectional error detection (AUED) technique capable of detecting multiple unidirectional errors. The SEDC scheme exploits data segmentation and parallel encoding features for assigning code words. Consequently, the SEDC scheme can be scaled to any binary data length “n” with constant latency and less complexity, compared to other AUED schemes, hence making it a perfect candidate for use in big data processing hardware. We also present a novel area, delay, and power efficient, scalable fault secure checker design based on SEDC. In order to show the effectiveness of our scheme, we <mml:math xmlns:mml=http://www.w3.org/1998/Math/MathML id=M1><mml:mo stretchy=false>(</mml:mo><mml:mn fontstyle=italic>1</mml:mn><mml:mo stretchy=false>)</mml:mo></mml:math> compared the cost of hardware-based fault tolerance with an existing software-based fault tolerance technique used in HDFS and <mml:math xmlns:mml=http://www.w3.org/1998/Math/MathML id=M2><mml:mo stretchy=false>(</mml:mo><mml:mn fontstyle=italic>2</mml:mn><mml:mo stretchy=false>)</mml:mo></mml:math> compared the performance of the proposed checker in terms of area, speed, and power dissipation with the famous Berger code and m-out-of-2m code checkers. The experimental results show that <mml:math xmlns:mml=http://www.w3.org/1998/Math/MathML id=M3><mml:mo stretchy=false>(</mml:mo><mml:mn fontstyle=italic>1</mml:mn><mml:mo stretchy=false>)</mml:mo></mml:math> the proposed SEDC-based hardware-level fault tolerance scheme significantly reduces the average cost associated with software-based fault tolerance in a big data application, and <mml:math xmlns:mml=http://www.w3.org/1998/Math/MathML id=M4><mml:mo stretchy=false>(</mml:mo><mml:mn fontstyle=italic>2</mml:mn><mml:mo stretchy=false>)</mml:mo></mml:math> the proposed fault secure checker outperforms the state-of-the-art checkers in terms of area, delay, and power dissipation." @default.
• W2806806218 created "2018-06-13" @default.
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• W2806806218 date "2018-06-07" @default.
• W2806806218 modified "2023-10-08" @default.
• W2806806218 title "SEDC-Based Hardware-Level Fault Tolerance and Fault Secure Checker Design for Big Data and Cloud Computing" @default.
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• W2806806218 doi "https://doi.org/10.1155/2018/7306837" @default.
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