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- W2806975955 abstract "Summary In this paper, a low‐power and high‐resolution latch‐based time‐to‐digital converter (TDC) based on a multistage scheme is proposed. The proposed multistage TDC includes coarse, middle, and fine stages. The coarse stage is a new design of the flash TDC that is implemented by latches without using the delay cell. Also, the middle stage is a new design of the Vernier TDC with employed latches. The fine stage comprises parallel latches with different input loads." @default.
- W2806975955 created "2018-06-13" @default.
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- W2806975955 date "2018-05-27" @default.
- W2806975955 modified "2023-09-27" @default.
- W2806975955 title "Low-power, latch-based multistage time-to-digital converter in 65 nm CMOS technology" @default.
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- W2806975955 doi "https://doi.org/10.1002/cta.2468" @default.
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