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- W2807631814 abstract "Resilient circuits based on timing error detection and correction can mitigate the timing margin effectively, but usually at a cost of extra area overhead. One of the major sources of area overhead is short-path padding (hold time fix), which is much severer than in traditional IC design for near-threshold operation. Therefore, we propose an insertion methodology by using transmission gates to extend short-paths, which decreases area overhead than traditional resilient methods. Because the clock-controlled transmission gate (CTG) can extend all the short paths by half a clock when working as a transparent-low latch, the short-paths problem is solved. Besides, as the transmission gates synchronize the multiple short paths, it decreases the invalid flipping of combinational logic, which reduces the glitch power. Applied on a SHA-256 algorithm circuit in a 28nm CMOS process with 0.55V supply, the proposed technique reduces the area overhead a lot compared to the conventional short-path padding techniques. For combinational circuit, its area reduces from 153.34% to 4.43%, and for sequential circuit area, it reduces from 124.33% to 19.33%." @default.
- W2807631814 created "2018-06-13" @default.
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- W2807631814 date "2018-05-30" @default.
- W2807631814 modified "2023-09-24" @default.
- W2807631814 title "Short-path Padding Method for Timing Error Resilient Circuits based on Transmission Gates Insertion" @default.
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- W2807631814 doi "https://doi.org/10.1145/3194554.3194600" @default.
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