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• W2809938152 abstract "An investigation into the increased leakage currents and reduced blocking voltages associated with 1450°C lifetime enhancement oxidation for the 4H-SiC p-GTOs is presented. Roughening of the 4H-SiC surface due to localized crystallization of SiO 2 , or crystobalite formation, during the high temperature oxidation was identified as one of the main causes of this issue. A factor of 30 difference in permeability to O 2 between amorphous SiO 2 and crystobalite caused uneven oxidation, which resulted in significant roughness. This roughness, placed at the metallurgical junction between the gate and the drift layer, where the E-field is greatest, is believed to be responsible for the premature breakdown characteristics. A 2-step lifetime enhancement process, which moves this roughness to the lower E-field region of the device was introduced to alleviate this issue. A 15 kV 4H-SiC p-GTO with the 2-step lifetime enhancement process demonstrated a significant reduction in V F over the 1300°C oxidized devices, without any impact on blocking characteristics." @default.
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• W2809938152 date "2018-06-01" @default.
• W2809938152 modified "2023-10-09" @default.
• W2809938152 title "Blocking Performance Improvements for 4H-SiC P-GTO Thyristors with Carrier Lifetime Enhancement Processes" @default.
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• W2809938152 doi "https://doi.org/10.4028/www.scientific.net/msf.924.633" @default.
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