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- W2810101711 abstract "This paper proposes a novel architecture for a scalable FPGA-based floating-point Gaussian filtering core. The core not only is able to accept floating-point kernels but also allows the kernels to be modified in both size and values at runtime. The proposed floating-point Gaussian filtering core is described with Verilog-HDL and is able to implement on various FPGA families. We schedule the operations of functional units inside the core in a pipeline model to improve performance. The core can be used for a 1D or a 2D Gaussian filtering with a simple wrapper. We conduct multiple experiments with various FPGA families. Experimental results show that our core can work at up to 224 MHz when implemented on a Xilinx Virtex 7 xc7vx485 device. Using this device, our core is able to perform a 2D Gaussian filtering for 40 or 11 7201280 images per second with a 3 3 or a 11 11 floating-point kernel, respectively" @default.
- W2810101711 created "2018-07-10" @default.
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- W2810101711 date "2017-11-01" @default.
- W2810101711 modified "2023-09-26" @default.
- W2810101711 title "A Scalable FPGA-based Floating-Point Gaussian Filtering Architecture" @default.
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- W2810101711 doi "https://doi.org/10.1109/acomp.2017.27" @default.
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