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• W2835672264 abstract "We present a fractional-N phase-locked loop (PLL) with an option to operate either in single-loop or in dual-loop configuration. The PLL is composed of two chips: a voltage controlled oscillator (VCO) chip and a synthesizer chip that are integrated on one printed circuit board. In the synthesizer chip, a chirp generation circuit is included for frequency-modulated continuous-wave (FMCW) radar systems. The measurement results reveal that in the steady state the dual-loop operation is superior over single-loop operation due to its lower in-band phase noise. This makes it attractive for FMCW radar using slow frequency ramps. By contrast, in the case of fast frequency ramps the single-loop configuration is preferred due to its higher VCO gain resulting in a faster frequency settling. The circuits are fabricated in a 0.13 μm SiGe BiCMOS technology and are well suited for highly integrated FMCW radar systems at 80 GHz. They offer high flexibility in programming ramp type, ramp duration and modulation bandwidth." @default.
• W2835672264 created "2018-07-19" @default.
• W2835672264 creator A5026083046 @default.
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• W2835672264 date "2018-05-01" @default.
• W2835672264 modified "2023-10-16" @default.
• W2835672264 title "A comparison of two frequency synthesizer architectures in SiGe BiCMOS for FMCW radar" @default.
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• W2835672264 doi "https://doi.org/10.23919/mikon.2018.8405218" @default.
• W2835672264 hasPublicationYear "2018" @default.
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