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• W2877345093 abstract "Summary This paper presents efficient and fast hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on extremely fast complete differential addition and doubling formulas. These new complete differential addition formulas are performed for general and special cases of BECs with cost of 5 M + 4 S + 2 D and 5 M + 4 S + 1 D , respectively, where, M , S , and D denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of the BECs, proposed structures are implemented based on 3 and 1 pipelined digit‐serial Gaussian normal basis multipliers. In the design by 3 multipliers, computation of point addition and point doubling is performed concurrently. But in the second implementation for low‐cost design with low number of hardware resources, these computations are implemented by 1 multiplier. Also, in the special case of BECs, 2 structures are proposed for achieving the highest degree of parallelization and utilization of resources by using 3 and 2 field multipliers. Implementation results of the proposed architectures based on Virtex‐5 XC5VLX110, Virtex‐4 XC4VLX100, and Arria‐10 10AX115U4F45I3SG FPGAs for 2 fields and are achieved. The results show improvements in terms of execution time, area, and efficiency for the proposed structures compared with previous works." @default.
• W2877345093 created "2018-07-19" @default.
• W2877345093 creator A5017337821 @default.
• W2877345093 date "2018-07-06" @default.
• W2877345093 modified "2023-09-26" @default.
• W2877345093 title "Efficient hardware implementations of point multiplication for binary Edwards curves" @default.
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• W2877345093 doi "https://doi.org/10.1002/cta.2498" @default.
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