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• W2887715041 abstract "This study proposes a single bit-line and disturbance-free static random-access memory (SRAM) cell for ultra-low voltage applications. SRAM cell with read-decoupled and cross-point structure addresses both the read-disturb and half-select stability issues; nevertheless, the write-ability is degraded due to the stacked pass transistors. In this study, the authors propose a single-ended 8T bit-cell and dual word-line control technique that can simultaneously improve the read stability, half-select stability, and write-ability without additional peripheral circuits, which is advantageous for bit-interleaved ultra-low voltage operations. A 4 kb test chip was implemented in a 90 nm complementary metal–oxide–semiconductor process to verify the proposed design. Silicon measurements indicate that the proposed design can operate at a voltage as low as 360 mV with 2.68 μW power consumption." @default.
• W2887715041 created "2018-08-22" @default.
• W2887715041 creator A5015109763 @default.
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• W2887715041 date "2018-10-29" @default.
• W2887715041 modified "2023-09-27" @default.
• W2887715041 title "Single bit‐line 8T SRAM cell with asynchronous dual word‐line control for bit‐interleaved ultra‐low voltage operation" @default.
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• W2887715041 doi "https://doi.org/10.1049/iet-cds.2018.5150" @default.
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