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• W2887823254 abstract "This dissertation addresses the problem of global synchronization of complex SoC in the context of deeply submicron CMOS technologies. Nowadays, to circumvent the difficulties associated with conventional clock distribution techniques (e.g. tree, mesh) in synchronous systems, the designers wishing to go on with the Globally Synchronous paradigm are turning toward clocking techniques breaking away from conventional approaches (e.g. distributed oscillators, stationary waves, coupled oscillators, programmable delays). This study is situated on this research axis. In this research we studied and elaborated a global distributed clocking system for a highly reliable synchronous circuit. This clocking scheme is based on a network of oscillators coupled in phase. Inside each synchronous clocking domain, there is one oscillator that generates the local clock. To synchronize the oscillators (i.e. domains), each one of them is controlled by an All-Digital Phase Locked Loop (ADPLL), realizing a phase coupling between the oscillators of neighboring zones. During this research we have developed the specifications and selected an architecture of the network. A theoretical model of the system has been established in a collaboration with CEA-LETI and Supelec laboratories in the framework of ANR HODISS project. We have analyzed the behavior of the system in simulations on different abstraction levels, investigated the stability conditions of its synchronous operation. An All-Digital Phase Locked Loop (ADPLL) has been proposed for the role of an elementary node of distributed clocking network. The use of ADPLL permits to circumvent difficulties of implementation, which are usually associated with analog PLL. We have designed the main blocks of the ADPLL: a Digitally-Controlled Oscillator (DCO), a Phase-Frequency Detector (PFD) and an error processing block. A cell-based design technique has been adapted for the design of DCO layout. This technique significantly reduced the complexity of the oscillator's implementation. The remaining blocks have been designed in a common digital design flow. In order to reduce the risks associated with silicon implementation, the system has been validated in a FPGA prototyping platform. The results of the measurements showed that clocking network behaves as predicted by the theory and simulations. Two prototype circuits have been designed, implemented and tested in a 65 nm STMicroelectronics CMOS technology. The first one is a proof of concept of a designed highly linear and monotonous DCO. The measured parameters of oscillator showed the compliance with specifications. The measured performance demonstrated the <15 ps rms jitter, while consuming 6.2 mW/GHz with 1.1 V supply voltage. The tuning range of the oscillator is 999-2480 MHz under 10 bit resolution. The second chip is a 4x4 node clocking network which consists of 16 distributed ADPLLs. Each of them employs a designed earlier DCO, PFD and error processing block. The experiments showed that proposed technique of distributed clock generation is feasible in a real CMOS chip environment. The measured performance demonstrated the timing error between neighbor oscillators less than 60 ps, while power consumption is 98.47 mW/GHz." @default.
• W2887823254 created "2018-08-22" @default.
• W2887823254 creator A5000777718 @default.
• W2887823254 date "2013-03-25" @default.
• W2887823254 modified "2023-09-28" @default.
• W2887823254 title "Distributed clocking for synchronous SoCs" @default.
• W2887823254 hasPublicationYear "2013" @default.
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